The present invention relates to integrated circuits, and more particularly to integrated circuits having reduced leakage current.
As circuit dimensions continue to shrink, power dissipation due to leakage current is becoming an ever greater problem. Leakage-current-induced power dissipation in mobile devices such as cell phones reduces battery life, thereby inconveniencing users by requiring more frequent re-charges. Ideally, a transistor in a digital integrated circuit acts like a switch, being either in a conductive (on) state or a non-conductive (off) state. However, transistors always conduct some amount of leakage current in the off state. As process technology advances into the 90 nanometer (nm) or 65 nm dimensions and smaller, the ability to close the channel between source and drain in a transistor weakens such that “subthreshold” leakage current continues to flow between the source and drain even when the transistor is turned solidly off.
Some approaches to mitigate subthreshold leakage current include lengthening the channel. However, that approach reduces achievable component density, thereby obviating one of the major advantages of modem process technology. Rather than lengthen the channel, other approaches use multiple gates, which increases process complexity and still reduces component density. Accordingly, there is a need in the art for integrated circuits having improved leakage current reduction.